x y
•
yxz +
x, y, z
. add.s
m68k-as
HEX
add.abs
HEX
HEX
S0 06 0000484452 1B
S2 14 000000 303900000018D0790000001A33C00000 14
S2 0C 000010 001C40484E720000 7F
S2 0A 000018 000A00140000 BF
S5 03 0003 F9
S8 04 000000 FB
S0 06 0000484452 1B
S2 14 000000 303900000018D0790000001A33C00000 14
S2 0C 000010 001C40484E720000 7F
S2 0A 000018 000A00140000 BF
S5 03 0003 F9
S8 04 000000 FB
S0 06 0000484452 1B
S2 14 000000 303900000018D0790000001A33C00000 14
S2 0C 000010 001C40484E720000 7F
S2 0A 000018 000A00140000 BF
S5 03 0003 F9
S8 04 000000 FB
1.
x → 0x000018
y → 0x00001a
z → 0x00001c
2. HEX
HEX
.data
HEX
S0 06 0000484452 1B
S2 14 000000 303900000018D0790000001A33C00000 14
S2 0C 000010 001C40484E720000 7F
S2 0A 000018 000A00140000 BF
S5 03 0003 F9
S8 04 000000 FB
HEX
.text)
HEX
68000
C
68000
y
x, y, z 2
yxz +
z
x, y, z 2
y
z
68000
x,y,z2
68000
68000
2
1010
2
2010
y
x, y, z
2
010
z
68000
2
1010
2
2010
y
x, y, z
2
010
z
CPU
10
10, 20
16
0x0a, 0x14
LSI
CPU
RAM)
(address bus)
(data bus)
(control bus)
R/W
R: Read
W: Write
CPU
RAM)
R/W
CPU
0x1a
0x1a, 0x1b
RAM)
CPU
0x1c
R/W
RAM)
(address bus)
(data bus)
(control bus)
R/W
R: Read
W: Write
CPU
Arithmetic and Logic Unit
CPU
R/W
Instruction Register
Instruction Decoder
Control Unit
Program Counter
+
Registers
Arithmetic and Logic Unit
CPU
R/W
Instruction Register
Instruction Decoder
Control Unit
Registers
Program Counter
CPU
Registers
Program Counter
CPU
CPU 68000
1.
2.
3.
,
4.
Registers
Program Counter
CPU
CPU 68000
(data
registers)
D0
D1
D2
D3
D4
D5
D6
D7
31 16 15 8 7 0
(address
registers)
A0
A1
A2
A3
A4
A5
A6
31 16 15 0
31 16 15 0
A7
A7
(user stack
pointer,
supervisor stack
pointer)
31 24 23 0
(program
counter)
15 8 7 0
(status
register)
CCR
PC
SP
SR
32
32
32
16
32
Arithmetic and Logic Unit
CPU
R/W
Instruction Register
Instruction Decoder
Control Unit
Program Counter
+
Registers
Arithmetic and Logic Unit
CPU
Registers
0x1a
0x1a, 0x1b
d0
d0
0x1a
0x1a, 0x1b
d0
0x1c
0x1c, 0x1d
2
d0
0x1e
0x1e, 0x1f
→ d0
d0
→ d0
→ d0
→ d0
d0
• CPUCentral Processing Unit;
